ADTRAN TSU LT User Manual download pdf (Page 52)

Chapter 7 Test Menu TSU LT User Manual

The self-test includes the following board-level tests, in this order:

1. RAM tests; EPROM checksum

2. On-board data path; sending a known test pattern through an on-board loop

3. Front panel LED verification

4. Phase lock loop verification. If a failure is detected, note the failure number and contact ADTRAN

Technical Support.

PORT TESTS

These two tests (DTE L

OOPBCK

and D

ATA

OOPBCK

) control the activation of a DTE loopback and a data

loopback (see Figure 7-4). The

DTE L

OOPBK

loops data received at the V.35 interface back towards the

DTE. The

ATA

OOPBACK

test the data is looped back just before going out the V.35 interface.

Figure 7-4. Port Loopback Tests

Executing self-test disrupts normal data flow and prevents remote communication until the

self-test is completed (approximately five seconds).

(NI)

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ADTRAN TSU LT User Manual Page 52